TSMC Details Apple’s M1 Ultra UltraFusion Interconnect

The founder has mobilized its InFO-LSI technology to interconnect the two M1 Max chips.

In March, Apple presented its M1 Ultra, a chip that combines two M1 Max. The UltraFusion interconnect enables 2.5 TB/s bandwidth between the two chips. To achieve this, TSMC, responsible for manufacturing the processor in 5 nm, does not mobilize its CoWoS-S packaging technology (chip-on-wafer-on-substrate with silicon interposer) but InFO_LSI (integrated fan-out with local silicon interconnect). Apple’s chip is one of the first to benefit from this.

Image 2: TSMC details Apple's M1 Ultra UltraFusion interconnect
Apple

TSMC’s CoWoS-S packaging is a proven technology used by a number of the foundry’s customers. This is not the case with InFO, which has been in the test phase for several years but was due to reach the qualification phase in the first quarter of 2021. In any case, Tom Wassick, a professional in the packaging engineering of semiconductors, revealed on his Twitter account that the M1 Ultra was well designed from this technology. He holds this information from TSMC, obtained as part of the International Symposium on 3D IC and Heterogeneous Integration. Tom Wassick also shared the slide above.

Apple and Intel, first to adopt TSMC’s 2nm engraving

A cheaper solution

Concretely, the InFO-LSI technology combines a local silicon interconnection (LSI) and a redistribution layer (RDL). The main advantage of InFO-LSI over CoWoS-S is its lower cost. As our de Tom’s Hardware US explains, CoWos-S requires the use of massive interposers made entirely of silicon and therefore quite expensive; InFO_LI makes do with localized silicon interconnects. The use of CoWoS-S technology is justified for certain products requiring the interconnection of numerous chips, often with HBM memory. However, this is not the case for the M1 Ultra, which combines “only” two M1 Max chips, which moreover without HBM memory.

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Sources: Tom’s Hardware US, Itigic, AnandTech

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